CPUCooL Optimization

For AMD K6 CPU’s
Write Allocation To optimize the cache strategy of L2 cache.
Data Prefetch If enabled, cache misses initiated by a memory read within a 32 byte cache line are conditionally followed by cache-line fetches of the other line in the 64 byte sector
Write Combining To enable to combine up to four byte accesses to a long word access. There are two possibilities:Global: It enables the CPU to write to any memory without write ordering.Speculative: is an restriction of global. Write ordering is done in any memory except the memory of the frame buffers and an external EWBE signal
EWBE Enhance Out of order writing to the L1 Cache.
Frame Buffer To optimize the access of the frame buffer in the graphics card. There are two frame buffers which could be optimized separately

Optimizations for Intel CPU’s
Low Power For Intel Pentium processor to enable low power mode (default off)
Low Power MMX For Intel Pentium II processors to enable low power mode (default)
L2 Strategie Number of clock cycles the CPU must wait before she could access the L2 cache again

Optimizations for Cyrix CPU’s

Write Allocation To optimize the cache strategy of L2 cache
Write Back Cache Set strategy for second level cache
IO Recovery Time Set IO recovery time to 0 or to max.
Linear Burst Chip set must support it. Be careful
Cached Directory For old Cyrix processors only
CPU ID CPU ID switch on
Negate Lock Do not wait for floating point unit
Suspend on Halt To enable power saving switch it on.
Framebuffer Sets the CPU cache buffer to the framebuffer of graphics card